1. Field of the Invention
The present invention relates to a counter circuit including a plurality of one-bit counters. More particularly, it relates to a counter circuit with an operational test function.
2. Description of the Related Art
In a conventional counter circuit which comprises a plurality of one-bit counters and has a test function, serial test data is input and the binary digits of the data are written in the respective one-bit counters. Further, the binary counts of the respective one-bit counters can be read out as serial data. Specific numeric values are written in the respective counters, and after the counters finish their counting operations, the binary counts of the counters are read out to check, from those counts, whether the counting operations could be performed normally.
FIG. 3 shows an example of such a conventional counter circuit. This is a four-bit counter circuit comprising four one-bit counters corresponding to the number of bits of the binary count. The counter circuit includes serial data control lines, a serial data input line and a serial data output line.
A counter input signal is input commonly to the clock input terminals CK of the respective counters as a clock signal for shifting data. A carry signal output terminal Y of each counter is connected to a carry signal input terminal A of the next stage. Note that a high level signal is input to the terminal A of the counter 31. An output terminal Q of each counter is connected to a data input terminal DIN of the next-stage counter. The data input terminal DIN of the counter 31 is an input terminal of serial data. A serial data control signal is input commonly to a control terminal SCAN of each counter. When this control signal goes to the high level, this counter circuit operates in the same manner as a shift register. More specifically, serial data applied to the data input terminal DIN of the counter 31 is input each time a counter input signal (clock signal) is input, and passes through the counters 31 to 34, and is output from the output terminal.
When this counter circuit is tested, the one-bit counters 31 to 34 are tested one after another. Each time one of the counters is tested, serial data needs to be input and output. As for the number of clock signals to be input to the counter circuit, if the number of bits of the counter circuit is N (N=4 in the example of FIG. 3), it is necessary to provide N clock pulses for input to one counter, a clock pulse for a counting operation, and N clock pulses for output of the serial data. Therefore, the total number of clock pulses is 2N+1. This applies to each one-bit counter, so that the total number of clock pulses is (2N+1) N, hence, 2.sup.2 +N. If the number of counting operations conducted to improve the reliability of the test is I, the total number of clock pulses is 2N.sup.2 +IN.
As described above, with the conventional counter circuit, input and output operations of serial data are required for every test of each one-bit counter. Therefore, the total number of clock pulses necessary for a test is proportional to the square of the number of bits of the counter circuit. For this reason, the time required for a test is also proportional to the square of the number of bits. Thus, as the number of bits of a counter circuit increases, the time necessary for a test becomes quite long. The reliability of a test varies with a combination of data written into each one-bit counter. Therefore, improving the reliability of the test with the combination of data will require a longer test time.